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Expanding the Memory Limits with CXL Software Stack - Vandana Salve, Micron

Expanding the Memory Limits with CXL Software Stack - Vandana Salve, Micron With the increasing memory requirements for AI/ML/HPC services both in terms of bandwidth and capacity, memory is playing a significant role in power, performance and TCO for these services. Emerging CXL devices can help expand bandwidth and capacity in these environments leading to improved performance. CXL is an open interconnect standard that increases memory capacity and bandwidth and enables lower latencies, it leverages the PCIe 5.0 physical layer infrastructure to create a common memory space across the host and all devices. CXL switching connects multiple hosts and memory devices, providing low-latency, high-bandwidth interfaces between various CXL devices such as CPU, GPU and memory modules The presentation start with introduction to CXL, covering the use cases of bandwidth and capacity expansion and then deep dives into the Linux software stack with support for memory tiering and memory interleaving. Topics to cover: Introduction to CXL Current Use cases : Bandwidth and capacity expansion The Software stack for CXL environment CXL Type 3 devices memory expansion CXL : Memory switching and pooling CXL: Memory tiering CXL : Memory interleaving