Скачать с ютуб More cache for less cash: CXL Memory Bandwidth and Capacity Expansion in Software Caches в хорошем качестве

More cache for less cash: CXL Memory Bandwidth and Capacity Expansion in Software Caches

Presented by Don Moon (SK hynix) | Daniel Byrne (Intel) | Sounak Gupta (Intel) With the increasing memory requirements for AI/ML/CDN/Web services both in terms of bandwidth and capacity, memory is playing a significant role in power, performance, and TCO for these services. Emerging CXL devices can help expand bandwidth and capacity in these environments leading to improved performance. In this work, we evaluate the performance of CXL memory bandwidth and capacity expansion at the caching layer of these services. To enable CXL, we extend CacheLib, a general-purpose caching library from Meta, to support multiple byte-addressable memory tiers. In our design, the first tier is DRAM-backed memory, the second tier is CXL-backed memory, and the last level remains backed by NVM device. Compared to a system without CXL – we improve the throughput by reducing pressure on NVM layer and increase total cache hit ratio with additional CXL memory. Furthermore, our multi-tier CacheLib outperforms OS interleaving of DRAM/CXL memory in terms of throughput and reduces P99 latency.