Скачать с ютуб SSCS CICCedu 2019 - Digital PLL - Presented by Mike Shuo-Wei Chen в хорошем качестве

SSCS CICCedu 2019 - Digital PLL - Presented by Mike Shuo-Wei Chen

Abstract: Phase locked loop (PLL) has recently evolved into a more digital intensive architecture, which allows the designers to leverage Moore’s Law. It creates new opportunities in applying various digital signal processing techniques; however, it also inherits some implementation overhead compared to the conventional analog PLL. In this short talk, I will overview the latest trend of digital phase locked loop (DPLL), and several recent research outcomes, aiming to lower the overhead of DPLL implementation as well as enhance its performance beyond conventional analog PLL. Through validations from the proof-of-concept prototypes, they show some interesting directions for future DPLL evolution. Bio: Mike Shuo-Wei Chen received the B.S. degree from National Taiwan University, Taipei, Taiwan, in 1998 and the M.S. and Ph.D. degree from University of California, Berkeley, in 2002 and 2006, all in electrical engineering. He is an associate professor in Electrical Engineering Department at University of Southern California (USC) and holds Colleen and Roberto Padovani Early Career Chair position. As a graduate student researcher, he proposed and demonstrated the asynchronous SAR ADC architecture, which has been adopted today for low-power high-speed analog-to-digital conversion products in industry. After joining USC, he leads an analog mixed-signal circuit group, focusing on high-speed low-power data converters, bio-inspired/biomedical electronics, RF frequency synthesizers, DSP-enabled analog circuits and systems. His research group has been exploring new circuit architectures that excel beyond the technology limitation, as exemplified in their recent works in PA, ADC, DAC, and PLL. From 2006 to 2010, he has been a member of Analog IC Group at Atheros Communications (now Qualcomm), working on mixed-signal and RF circuits for various wireless communication products. Dr. Chen was the recipient of Qualcomm Faculty Award in 2019, NSF Faculty Early Career Development (CAREER) Award, DARPA Young Faculty Award (YFA) both in 2014, Analog Devices Outstanding Student Award for recognition in IC design in 2006 and UC Regents’ Fellowship at Berkeley in 2000. He also achieved an honourable mention in the Asian Pacific Mathematics Olympiad, 1994. In terms of services, Dr. Chen has been serving as an associate editor of IEEE Solid-State Circuits Letters (SSC-L), IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), as well as a TPC member of conferences in IEEE Solid-State Circuits Society, such as IEEE International Solid-State Circuits Conference (ISSCC), IEEE VLSI Circuits (VLSIC) Symposium, and IEEE Custom Integrated Circuits Conference (CICC).